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rev. 1.2 12/10 copyright ? 2010 by silicon laboratories si3452 q uad h igh -v oltage p ort c ontroller for p o e and p o e+ pse s features applications ? each si3452 high-voltage port controller supports four pse power interfaces ? programmable current limits for poe (15.4 w), poe+ (30 w), and proprietary systems (up to 40 w) per port ? i 2 c interface requires no external mcu for easy, low-cost management of 4 to 48 ports by the host system ? unique mixed-signal ic high-voltage component integr ation simplifies design, lowers power dissipation, minimizes external bom, and reduces pcb footprint ?? internal low-r on power fets with current-sense circuitry ?? integrated transient voltage surge suppressors ?? proprietary dv/dt disconnect sensing methods ? industrial (?40 to 85 c) operating temperature ? compact, 66 mm 2 , 40-pin qfn rohs-compliant package ? programmable architecture supports ieee 802.3af (poe) and ieee 802.3at (poe+) pses ?? programmable current limits for poe (350 ma) and poe+ (600 ma), and custom limits to 850 ma ?? per-port current and voltage monitoring for sophisticated power management and control ?? power policing mode ?? robust multi-point detection ?? supports 1-event and 2-event classification algorithms ? comprehensive, robust, fault- protection circuitry ?? supply undervoltage lockout (uvlo) ?? output current limit and short- circuit protection ?? foldback current limiting ?? dual-threshold thermal overload protection ?? fault source reporting for intelligent port management ? power over ethernet endpoint switches and midspans for ieee std 802.3af and 802.3at ? supports high-power pds, such as: ?? pan/tilt/zoom security cameras ?? 802.11n waps ?? multi-band, multi-radio waps ? security and rfid systems ? industrial automation systems ? networked audio ? ip phone systems and ipbxs ? metropolitan area networked waps, cameras, and sensors ? wimax asn/bts and cpe/odu systems ordering information: see page 31. pin assignments 40-pin qfn see "9. pin descriptions" on page 28. vee vee1 ain rbias vref agnd aout 1 2 3 4 5 6 7 agnd 8 dgnd vdd ad1 ad3 ad0 ad2 ad2 30 29 28 27 26 25 24 vout4 nc sda nc det4 scl gnd34 11 12 13 14 15 16 17 det3 18 vdd 19 39 38 37 36 35 34 33 vout1 int det1 ad0 rst gnd12 ad1 det2 vee4 10 nc 9 vee3 22 rst 23 ad3 21 vout3 20 32 vout2 31 vee2 si3452 (top view) 40 si3452
si3452 2 rev. 1.2 description when connected directly to the host system or configured in auto mode, each si3452 high-voltage port controller provides all of the critical circuitry and sophisticated power measurement functionality for the high-voltage interfaces of four comple te pse ports. the si3452 fully integrates ro bust, low-r on (0.3 ? typical) power mosfet switches, low-power dissipation current sensing circui try, and transient voltage surge suppression devices. the on-chip current sense circuitry and power mosfets provide programmable scaling of current limits to match either poe (350 ma, 15.4 w), poe+ (600 ma, 30 w), and extended (800 ma, 40 w) power requirements on a per- port basis. designed for use in endpoint pse (e.g., ethernet switches) or midspa n pse (e.g., inline power injectors) applications, each si3452 also performs the ieee-required powered device (pd) detection, classification, and disconnect functionality. the flexible architecture en ables powered device disconnec t detection using silicon labor atories' proprietary dv/dt disconnect sensing algorithm. dv/dt disc onnect is an alternative to dc discon nect that requires no additional bom components, does not dissipate extra device power, and fu lly interoperates with all powered devices. also provided are multi-point detection algorithms and per-port current and voltage monitoring. intelligent protection circuitry includ es power supply undervoltage lockout (uvlo), port output current limiting and short-circuit protection, thermal overload sensing and port shutdown, and transient voltage surge suppressors capable of protecting the si3452 from a variety of harsh surge events seen on the rj-45 interface. to maximize system design flexibility and minimize cost, each si3452 connects di rectly to a system host controller through an i 2 c serial interface, eliminating the need for an ex ternal mcu. the si3452 can be set to one of 12 unique addresses, allowing control of up to 48 ports on a single i 2 c bus. functional block diagram per port analog ad2 ad1 ad3 hv spi & port control vee1 vout1 aout gate control, current limit & foldback detection & classification dv/dt disconnect channel mode & limit control vref & central bias meas. mux pga det4 vout2 vout3 det3 det2 gnd12 agnd vdd vee3 thermal prot. rbias ad0 vee2 vee4 det1 vout4 current sense vref vee dgnd amux 10b adc temp sensor ain lv spi ad1 ad0 ad2 ad3 mcu core & pse fsm 256 byte sram 8 kbyte eprom i2c rst pll voltage regulator & monitor vdd agnd por wdt int gnd34 rst sda scl
si3452 rev. 1.2 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. pse system-level diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3. pse application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.1. detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2. classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.3. port turn-on and power fets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4. disconnect detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5. transient voltage surge suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.6. temperature sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.7. port measurement and monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.8. smbus/i 2 c interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5. register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 5.1. interrupt (registers 0x00? 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2. port event (registers 0x02?0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 5.3. port status (registers 0x06?0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4. port configuration (reg isters 0x0a?0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.5. command and return register s (registers 0x12?0x1c) . . . . . . . . . . . . . . . . . . . . .19 5.6. device status regi ster (0x1d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6. operational notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1. port turn on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2. changing the interrupt ma sk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.3. port voltage and current measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7. pcb layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8. firmware release notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 8.1. initialization time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.2. current limiting in 2x power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.3. i 2 c address ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.4. reading or writing unus ed registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10. package outline: 40-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 11. recommended pcb footpri nt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 12. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 12.1. evaluation kits and refe rence designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 13. device marking diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
si3452 4 rev. 1.2 1. electrical specifications unless noted otherwise, specificat ions apply over the operating te mperature range with vdd = +3.3 v and vee = ?48 v relative to gnd. vdd pins should be electrically shorted. agnd pins, dg nd, gnd12, and gnd34 should be electrically shorted (?gnd?). vee, vee1, vee2, vee3, and vee4 should be electrica lly shorted (?vee?). vport for any port is measured from gnd to the respective voutn. table 1. absolute maximum ratings 1 type description rating unit supply voltages vee to gnd ?62 to +0.3 v vdd to gnd ?0.3 to +3.6 v vdd1 to vdd2 ?0.3 to +0.3 v any vee to any othe r vee ?0.3 to +0.3 v any gnd to any other gnd ?0.3 to +0.3 v voltage on digital pins sda, scl, adn, rst , int (gnd ? 0.3) to (vdd + 0.3) v voltage on analog pins vref, ain, aout, rbias, osc (gnd ? 0.3) to (vdd + 0.3) v voutn, detn (vee ? 0.3) to (gnd + 0.3) v detn peak currents during surge events 2 5 a maximum continuous power dissipation 3 1.2 w maximum junction temperature 125 c ambient storage temperature ?55 to 150 c lead temperature (soldering, 10 seconds maximum) 260 c notes: 1. functional operation should be restricted to those conditions specified in table 2. functional operation or specification compliance is not implied at these cond itions. stresses beyond those listed in absolute maximum ratings may cause permanent damage to the device. 2. see ieee std 802.3-2005, clause 33.4, for a description of surge events. 3. if all ports are on with 600 ma load, the power dissipation is <1.2 w. at 85 c ambient with the expected 32 c/w thermal impedance, the junction temperature would be 123.4 c, which is within the 125 c maximum rating.
si3452 rev. 1.2 5 table 2. recommended operating conditions description symbol test conditions min typ max unit ambient operating temperature t a ?40 ? 85 c thermal impedance* ja no airflow ? 32 ? c/w 1 m/s airflow ? 28 ? power supply voltages v ee supply voltage v ee for ieee 802.3af (15.4 w) apps. ?57 ?48 ?45 v for ieee 802.3at (30 w) apps. ?57 ?54 ?51 v dd supply voltage v dd 3.0 3.3 3.6 v power supply currents v ee supply current i ee all ports on, excluding load current. ? 3.7 6.0 ma all ports in shutdown mode ? 1 2 v dd supply current i dd ?814ma *note: modeled with six parts evenly spaced on a 30 x 120 mm 2 , four-layer board with 25 thermal vias to a vneg plane on the back. table 3. uvlo, and reset specifications description symbol test conditions min typ max unit v dd reset threshold v rst ?1.75 ? v v dd power-on ramp * ramp from 0 v to 3.0 v ? ? 1 ms rst input high voltage 0.7 x v dd ?? v rst input low voltage ? ? 0.8 v rst input leakage rst =0v ? ? 40 a reset time delay t rstdly time between end of reset and beginning of normal operation ??100ms reset assertion time t rst rst low time to generate system reset 15 ? ? s v ee monitor accuracy v eemon measured v ee relative to actual v ee for v ee (?44 to ?57 v) ?4 ? 4 % v ee uvlo threshold v uvlo point at which vee uvlo is declared. vee going negative vee going positive ?38 ? ?36 ?33 ? ?31 v *note: if vdd ramp time is slower than 1 ms, hold the reset pins low until vdd is above 3.0 v to insure proper reset operation.
si3452 6 rev. 1.2 table 4. detection specifications description symbol test conditions min typ max unit detection current limit i lim_det measured with detn shorted to gnd ?3 5ma detection voltage, when r det =25k ? v det1 v det2 v det3 ? ?10.0 ? ?4.0 ?8.0 ?4.0 ?2.8 ? ?2.8 v detection slew rate ? ? 0.1 v/ s detection probe duration t probe 10 ? 30 ms detection probe cycle time t det ??500ms minimum valid signature resistance r det_min 15 ? 19 k : maximum valid signature resistance r det_max 26.5 ? 33 k : resistance at which open circuit is declared r open 100 ? 400 k : resistance at which short circuit is declared r short 150 ? 400 w valid detect capacitance c det_valid ??150nf invalid detect capacitance c det_invald 10 ? ? f table 5. classification specifications description symbol test conditions min typ max unit class event voltage v class 0ma < i port < 45 ma ?20.5 ? ?15.5 v mark event voltage v mark 0ma < i port < 5 ma ?7 ? ?10 v classification current limit i lim_class measured with detn shorted to gnd 51 ? 100 ma classification current regions class 0 class 1 class 2 class 3 class 4 overcurrent 0 8 16 25 35 51 ? ? ? ? ? ? 5 13 21 31 45 ? ma classification delay t class_dly time from end of valid detect cycle to classification begin ?5?ms classification event time t cle width of valid v class probe for 1- event or 2-event classification 10 ? 30 ms mark event time t me width of mark between classification events ?8?ms
si3452 rev. 1.2 7 table 6. vout drive and power-on specifications description symbol test conditions min typ max unit max output resistance (port on) r on i port 720 ma ? 0.3 0.6 ? current limit i lim 1x mode, v port =v ee + 1 v 400 425 450 ma change in current limit ' i lim 1x mode, v port =v ee + 1v to ?30v 1 ?2 ? 2 % current limit i lim 2x mode, v port =v ee + 1 v 800 860 920 ma change in current limit ' i lim 2x mode, v port =v ee + 1v to ?40v 2 ?2 ? 2 % current limit i lim 1x mode or 2x mode, v port =?10v 60 ? ? ma overload current threshold i cut class 0 class 1 (class policing enabled) 3 class 2 (class policing enabled) 3 class 3 class 4 4 350 91 160 350 600 ? ? ? ? ? ? ? ? ? ? ma over current time limit 5 t ovld load current i cut or i lim 50 ? 75 ms voutn turn-on slew t rise 10% to 90% 15 70 ? s power turn on timing t pon time from end of valid detect to power on ??400ms voutn leakage cur- rent i out_leak port in shutdown ? ? 10 a notes: 1. t j >25 c, ?35 v over the full temperature range. 2. 1x mode current limit is enforced during the 60 ms t start time. 3. in auto mode, class policing is autom atically enabled. in manual mode, i cut must be programmed manually. see "5.4. port configuration (registers 0x 0a?0x11)" on page 18 for more information. 4. 600 ma is consistent with the ieee 802.3at draf t standard. i cut is user-programmable in 3.2 ma increments to over 800 ma for non-standard applications. 5. for 2x mode and extreme overload or short-circuit events, t ovld will dynamically decrease to prevent excessive fet heating. this is consistent with the 802.3at draft. table 7. dv/dt disconnect specifications description symbol test conditions min typ max unit load current to prevent disconnect i on 10 ? ? ma load current to guarantee disconnect i off dv/dt disconnect ? ? 2 ma disconnect delay t dcdv_dly time from i off load current to port turn off 300 ? 400 ms
si3452 8 rev. 1.2 table 8. port measurement and monitoring specifications description symbol test conditions min typ max unit port current measurement offset i offset 20 ma i port i cut . for final i port reading, add offset to% of reading tolerance. ?5 ? 5 ma port current measurement tolerance % tol ?4 ? 4 % table 9. smbus (i 2 c) electrical specifications vdd = 3.0 to 3.6 v description symbol test conditions min typ max unit input low voltage v il scl, sda pins ? ? 0.8* v input high voltage v ih scl, sda pins 2.2 ? ? v output low voltage v ol scl, sda pins, driving 8.5 ma ??0.6v input leakage current i l scl, sda pins ? ? 40 a *note: 0.85 v for t j > ?10 c. this ensures compatibility with si840x isolators with 3 k : pull up. for isolator compatibility over the full temperature rang e, use si860x isolators. table 10. address pin electrical specifications* vdd = 3.0 to 3.6 v description symbol test conditions min typ max unit input low voltage v il ad0, ad1, ad2, ad3 pins ? ? 0.8 v input high voltage v ih ad0, ad1, ad2, ad3 pins 0.7 x v dd ?? v input leakage current i h , i l ad0, ad1, ad2, ad3 pins ?10 ? 10 a *note: at power-up, these pins are logic inputs. a 10 k : pull up or pull down resistor is used for address selection. after address recognition, the pins are used for internal communications.
si3452 rev. 1.2 9 figure 1. i 2 c timing diagram table 11. smbus (i 2 c) timing specifications (see figure 1) vdd = 3.0 to 3.6 v description symbol test conditions min typ max unit serial bus clock frequency f scl 0?400khz scl high time t skh 600 ? ? ns scl low time t skl 1.3 ? ? s scl, sda rise time t r_scl 20 ? 300 ns scl, sda fall time t f_scl 20 ? 150 ns bus free time t buf between start and stop conditions. 1.3 ? ? s start hold time t sth between start and first low scl. 600 ? ? ns start setup time t sts between scl high and start condition. 600 ? ? ns stop setup time t sps between scl high and stop condition. 600 ? ? ns data hold time t dh 200 ? ? ns data setup time t ds 200 ? ? ns time from hardware or software reset until start of i 2 c traffic t reset reset to start condition ? ? 100 ms delay from event to int pin low or from clear-on- read to int pin high t int ?? 5ms notes: 1. not production tested ( guaranteed by design). 2. all timing references measured at v il and v ih . 3. the si3452 will stretch (pull down on) sck during the ack ti me period if required. the maximum scl stretching is 10 sec; so, scl only needs to be bidirectional for i 2 c bus speeds over 50 khz. scl d7 f sc l t r_scl t f_sc l t sk h sda t skl t st h t sps d6 d5 d4 d3 d0 t ds t dh star t bit stop bit t buf
si3452 10 rev. 1.2 table 12. interrupt (int ) specifications description symbol test conditions min typ max unit output low voltage v ol int pin driving 8.5 ma ? ? 0.6 v table 13. input voltage reference specifications description symbol test conditions min typ max unit nominal vref input ? 1.1 ? v reference tolerance ? ? 1 % vref loading input current ?10 ? +10 a
si3452 rev. 1.2 11 2. pse system-level diagrams figure 2. 4-port system with direct host connection 3. pse application diagrams figure 3. 4-port application diagram using dv/dt disconnect and i 2 c host interface si3452 high voltage interface i2c otp ram mixed signal resources pse state machines and measurement subsystem host controller i2c 4 ports of poe+ int sda scl rst si8405 digital isolator si3452 int rst scl sda vref si8405 bidirectional isolator host / switch vdd dgnd agnd det4 det3 det2 det1 vout1 vout2 vout3 vout4 rbias 44.2 k 1% vee port1 port2 port3 port4 to magnetics gnd12/34 vee[4:1] ad3 ad2 ad1 ad0 ad2 ad3 ad1 ad0 +3.3 v tie high or low to select address ?54 v 1.1 v (e.g. tlv431) 4x10 k :
si3452 12 rev. 1.2 4. functional description integrating four independent, high-voltage pse port interfac es, the si3452 high-voltage port controller enables an extremely flexible solution for virt ually any poe or poe+ pse application. the si3452 provides all of the high- voltage power over et hernet pse functions. each port of the si3452 in tegrates all high-voltage pse controller function s needed for a quad-port poe design, including the power mosfet, efficient current-sensing circuitry, transient voltage surge suppre ssor, and multiple detect and disconnect circuits. the external bom is typica lly only a single filter capacitor on each high-voltage port. when a pd device has been properly detected and classi fied, the port is powered by a ?54 v nominal supply with continuous monitoring of voltage and current for feedback to the host system. in addition to the required ieee features, th e si3452 includes many additional features: ? per port current / voltage monitoring and measurement ? support for 1-event and 2-event classification algorithms ? start up in shutdown or auto mode ? alternative a (typically used for endpoint systems) or alternative b (typically used for midspan systems) detection timing 4.1. detection the si3452 has per-port signature detec tion that satisfies the ieee std 80 2.3?-2005 specificat ions. however, by utilizing a 3-point voltage-forced dete ction method, the si3452 yields robu st recognition of valid and invalid powered device (pd) signatures, properly identifying si gnatures often mischaracter ized by other detection techniques. figure 4. pse sequencing (3-point detection followed by 2-event classification and powerup) vport relative to gnd the detection circuitry performs the f unction of setting the output voltage on any channel to the proper value for detection or classification and then measuring the resulting line current. a typical detection cycle consists of a pplying 4 v, then 8 v, then 4 v again with the current limit set to 3 ma. the current is measured after an appropriate settling time. for a valid pd, the detection signature must be compliant with the detection voltage both increasing and decreasing. 3 point detection 2 event classification port powerup
si3452 rev. 1.2 13 4.2. classification following a successful pd detection, the classification phase will be automatically initia ted in all operational modes. during this phase, a sing le measurement will be made at 18 v to determine how much power the pd device will draw under maximum loads per the ieee 802.3af and 802.3at sta ndards. the current limit during this test mode is 60 ma nominal. the si3452 supports 1-event and 2-event classification. when operating in poe (< 15.4 w) mode, 1-event classification is used. operation in poe+ (>15.4 w) mode results in 2-event classification probes. the 1-event classification is compliant to ieee standard 802.3-2005. 2- event classification is comp liant to draft ieee p802.3at. 4.3. port turn -on and power fets the fet is turned on with a gate drive that results in a very low-noise turn -on waveform with a slew rate of less than 1 v/sec (see figure 5). the power fet switch on each port has been sized to have a typical on resistance of approximately 0.3 ? . the shunt resistor for current measurement has also been set to 0.1 ? . including interconnection and process variation, the total resistance to vee for a port that is on is 0.6 ? (max). this limits the maximum power dissipation per channel to < 250 mw when the operating current is 600 ma, the maximum current allowed by the ieee 802.3at poe+ standard. the fet has a programmable operating current limit. each channel can be set to support output currents of 400 ma or 800 ma minimum. in addition to the normal current limit, there is a short ci rcuit current shutdown approximately 25% greater than the nominal current limit. if there is a transient current surge where the current ramps up faster than the programmed current limit can respond, the gate drive voltage is clamped immediately to v ee . the clamp is enabled for at least 10 s, which allows the normal current circuitry to respond. another important protection feature is foldback current limiting. when v out is near v ee , the current limit is at maximum. as the v ds of the driver switch increases (and v out is closer to ground), the current limit goes to its lowest level. the amount of the foldback current is scaled proportionally with the programmed current limit. figure 5. turn-on waveform?vport relative to gnd
si3452 14 rev. 1.2 4.4. disconnect detection the dv/dt disconnect function can be used to detect a disconnected device withou t using dc disconnect or ac disconnect. in dv/dt disconnect mode, the fet current limit is swit ched to 7.5 ma. if the voltage across the fet increases, a load is assumed to be present, and the fet current limit is au tomatically switched back to its pre-selected value. if, after 350 ms, the fet voltage has not increased, there is no load present, and the fet is turned off. in addition to operating in a manner functionally di stinct from dc disconnect, dv/dt disconnect requires no additional external components and fully interoperates with all powered device dc maintain power signatures. for more information, see "an399: dv/dt dis connect and the ieee 802.3 poe standard". 4.5. transient voltage surge suppression the si3452 features robust on-chip surge protectors on each port; this is an industry first. this unique protection circuitry acts as an active device that can withstand lightning-induced transients as well as large esd transient events. when the port voltage exceeds its protection limit and the current reaches a triggering threshold, current is shunted from the port to the ground pins. internal circuitry is provided to protect the line outputs from externally-coupled fault currents. these are transient currents of up to 5 a peak. the operation of the protection circuits depends on the operating mode of the channel switch and the direction of the fault current. the clamping operation is performed on the detect pin. the switch itself will also be protected by the current limit. if the transient lasts long enough to heat up the die, then the temperature sense circuit will shut of f the switch, and all the fault current will flow through the clamp diode. 4.6. temperature sense a temperature sense signal is used in conjunction with the current limit status signals from the gate drive blocks. any channel that is generating excess heat is assumed to be operating in current limit mode, with both high voltage drop and high current. if the port is in poe mode , an overload will generally not result in thermal shutdown before the 60 ms i cut period. if the port is in poe+ mode, an overload may cause the port to shut down prior to the 60 ms i cut period. in either case, the event is reported as i cut . the faster shutdown in poe+ mode is consistent with and specifically allowed by the 802.3at draft and provides much more robust ov erload protection than is possible with external fets. in addition, there is a thermal shutdown if the package temperature exceeds 120 c. if this threshold is reached, all output drivers are turned off and detection modes are di sabled. this secondary thresh old limit guards against the possibility that the over heating is not caused by a driv er operating in current limit. 4.7. port measurement and monitoring vee monitoring in conjunction with po rt current monitoring allows measurement of port power. port power monitoring, dynamic power allocation via lldp*, and po rt power policing allow efficient power supply sizing. the si3452 is factory-calibrated and temperatur e-compensated for the following measurements: ? port current measurement. these measurements are auto-ranged and scaled to a 16 bit number at 100 a per bit. port current accuracy is 4% 2 ma. ? v ee is measured with a scale of 64 v. the measurement is reported as a 16-bit number scaled at 1 mv per bit. v ee measurement accuracy is 4% over the valid v ee range. *note: lldp = link layer discovery protocol. refer to ieee 802.3at (draft) and ieee 802.1ab for more information.
si3452 rev. 1.2 15 4.8. smbus/i 2 c interface description the i 2 c interface is a two-wire, bidirectional serial bus. the i 2 c is compliant with the system management bus specification (smbus), version 1.1 and compatible with the i 2 c serial bus. reads and writes to the interface by the system controller are byte-oriented with the i 2 c interface autonomously controlling the serial tr ansfer of the data. a method of extending the clock-low dura tion is available to accommodate devi ces with different speed capabilities on the same bus. the i 2 c provides control of sda (serial data), scl (serial clock) generati on and synchronization, arbitration logic, and start/stop control and generation. a typical i 2 c transaction consists of a start condition followed by an address byte (bits7?1: 7-bit slave address; bit0: r/w direction bit), one or more bytes of data, and a stop condition. each byte that is received (by a master or slave) must be acknowledged (ack) with a low sda du ring a high scl (see figure 6). if the receiving device does not ack, the tran smitting device will read a nack (not ackn owledge), which is a high sda during a high scl. the direction bit (r/w) occupies the least-significant bit posi tion of the address byte. the direction bit is set to logic 1 to indicate a "read" operation and cleared to logic 0 to indicate a "write" operation. all transactions are initiated by a master, with one or more addressed slav e devices as the target. the master generates the start condition and then transmits the slave address and directio n bit. if the transaction is a write operation from the master to the slave, the master transmits the data one byte at a time, waiting for an ack from the slave at the end of each byte. for read operations, the slave transmits the data waiting for an ack from the master at the end of each byte. at the end of the data transfer, the master generates a stop condition to terminate the transaction and free the bus. figure 6 illustrates a typical smbus/i 2 c transaction. silicon laboratories recommends the use of bidirectional digital isolat ors, such as the si840 x, to isolate the i 2 c communications interface between the si3452 high-voltage port controllers and the system host controller. figure 6. typical i 2 c bus transactions the si3452 does not support the alert response address (ara) protocol. polling is used to determine which controller is interrupting in an interrupt-driven system. 0 1 0 a3a2a1a0r/w# ack b y i c a7 a6 a5 a4 a 3 a2 a1 a 0 ack b y ic d7 d6 d5 d4 d3 d2 d1 d0 ack by ic st op by m aste r st art fixed ic address pin set ic add r ess slave address register address write data 010a3a2a1a0r/w# ack b y i c a 7 a6 a5 a4 a3 a 2 a1 a0 ack b y ic start fixed ic ad dr ess pin set ic ad dr e ss s lav e ad d re ss register address setup register address start 0 1 0 a3a2a1a0r/w# ack b y i c d7 d6 d5 d4 d3 d2 d1 d0 not ack by master stop by master fixed ic address pi n se t ic add r ess slave address register data transfer data to setup address write se quence read sequence
si3452 16 rev. 1.2 4.8.1. address pins pins with the same name must be externally c onnected and then tied high or low via a weak (10 k ? ) pull up or pull down to establish the device address at power up. the si3452 powers up in either auto mode or shutdown mode depending on the ordering part number. for more information, see "12. ordering guide" on page 33. 4.8.2. address format the address byte of the i 2 c communication protocol has the following format: ad3, ad2, ad1, and ad0 are the pi n-selected address bits (pull up = 1; pull down = 0). for the r/w bit, see figure 6. the device will also respond to the global addr ess, 0x30. the si3452 does not support bu s arbitration; so, a global read command will generally give an invalid result. global writes can be useful for initialization as well as for shutting down low-priority ports. table 16 lists the valid device addresses: table 14. address pin assignments pin # pin name 21 ad3 24 ad3 25 ad2 26 ad2 27 ad1 28 ad0 34 ad0 36 ad1 table 15. i 2 c address byte protocol bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 1 0 ad3 ad2 ad1 ad0 r/w table 16. address selection ad3 ad2 ad1 ad0 address valid 00000x20y 00010x21y 0010 ? n 0011 ? n 01000x24y 01010x25y 0110 ? n 0111 ? n 10000x28y 10010x29y 10100x2ay 10110x2by 11000x2cy 11010x2dy 11100x2ey 11110x2fy
si3452 rev. 1.2 17 5. register interface the register types are described in the following sections. refer to table 19 on page 20 for a complete map of the registers. 5.1. interrupt (registers 0x00?0x01) an interrupt (int pin low) is generated if any bit of the interrupt r egister (register 0x00) is true. the interrupt register contains the information about which port is generating the interrupt or if the interrupt is due to a global event. the port interrupt is generated by the port event register masked by the interrupt mask register. port event = (t start event and t start mask) or (ti cut event and ti cut mask) or (rgood_cls_event and rgood_cls_mask) or (det_com pl_event and det_compl_mask) or (pwrgood_change and pwrgood_change_m ask) or (penable_even t and penable_mask) the device event bit of the interrupt regist er is set if there is a change in the v ee or temperature status in register 0x1d. reading 0x1d clears the event. 5.2. port event (registers 0x02?0x05) this register contains bits that become true if the event has occurred. the registers are clear on read (cor) so that reading these registers will clear the int pin if the int pin is being held low due to a port event. ? t start is an event bit indicating an overload occurred for all but 5 ms of the initial 60 ms start up time. ? ti cut is an event bit indicating that an overload condition has existed for greater than 60 ms after the first 60 ms. ti cut has a 16:1 up/down counte r so that, if the overload is present at less than a 6.66% cycle, the port will not shut down. overload is defined as i>i cut or port voltage not within 2 v of v ee . the port is turned off on this event. a ti cut event is also generated if the port is shutdown due to an overload or due to the protection clamp turning on. if the port is set to auto mode, it will attempt to re -power after >750 ms if there is a good detection signature. ? rgood cls indicates classification has been completed. classi fication is only attempted after an rgood; so, if this bit is set, it indicates that detection gave an rgood and classi fication is complete. ? det compl indicates the completion of a detection cycle. normally, this bi t will be masked. the det complete bit is used for legacy detection via modified link pulses. if the link pulse is returned indicating a pd is present, then, normally, a detection is done, and the port is powered only if the result is not a short. in some cases, it may be desirable to deny power to a port where an overlo ad has been detected until the port is unplugged. in this case, the ropen result will be us ed to indicate the port ha s been unplugged and detection and classification can resume. ? disconnect event indicates a disconnect has occurred. dc powe r was removed due to the dv/dt disconnect. overload conditions or loss of v ee turns off ports but does not generate a disconnect event. ? pgood indicates the port has been turned on and did not shut down during the tstart time. ? penable indicates a port has been turned on. 5.3. port status (registers 0x06?0x09) these registers specify the port st atus. they are read-only registers. ? pwr good indicates that the port has been turned on and the port voltage is within 2 v of v ee . ? pwr enable indicates the port has been turned on. the three class status bits indicate the last classification re sult for that port. if a classification has not been done or if the port is shut down with no new classification result, the cla ss status is reported as unknown. the three detect status bits indicate the last detection result for that port. if a detection has not been done or if the port is shut down with no new detection result, the detection status is reported as unknown.
si3452 18 rev. 1.2 5.4. port configurat ion (registers 0x0a?0x11) these registers indicate the port conf iguration and are read/write registers. the port priority bit is set if the port is not high prio rity. low-priority ports are shut down when the shutdown low- priority ports command is issued. the ?poe+? bit specifies the dc current limit at either 425 ma or 850 ma nominal*. *note: the poe+ mode should be set correctly according to the electric al design of the pse circuit (transformer and conductor current carrying capacity). the poe+ port mode can safely be changed prior to port turn-on, but changes after port turn- on do not have an immediate effect and are not recommended. ?disconnect enable? must be set for power to be removed if there is a disconnect. ?port mode? is set according to table 17. i cut is the nominal current level at which the port will automatically power down if i cut is exceeded for 60 ms. it can be set with 3.2 ma resolution. the accuracy of current measurement is approximately 5%; so, i cut is normally set 7% higher than the supported current level. i cut is automatically set based on the classification result and poe+ mode. the automatically-set i cut level is appropriate for a 45 v mini mum system power supply for classes 0?3 and for a 51 v minimum power supply for poe+ mode. this feature is classification policing. if the si3452 is in the semi-auto mode, i cut will not be updated accord ing to the classificati on result. this means that if it is desired to set i cut at port turn-on, this should be done before the port is turned on. once a port is turned on, i cut can be changed dynamically. it is ofte n undesirable to use a low value of i cut during port turn-on because inrush can trigger the i cut event. for this reason, it is normal to allow the port to turn on with the automatic i cut setting and then later c hange this value after po rt current has stabilized and also if the pd and pse have negotiated for a different i cut value based on the poe l2 powe r negotiation protocol (lldp). the si3452 supports 2-even t classification as defined in the ieee 80 2.3at draft. 2- event classification is an alternative to l2 powe r management where the pse advertises it is capable of poe powering by generating two classification pulses. 2-event classification is only s upported for auto mode. if the si3452 is in auto mode and the first event classification re sult is class 4, the mark, second event, and second mark are performed. power is applied only if the second event is also class 4. if th e second event is not class 4, the classification error is reported, and the port will not power. if the port is in ma nual mode, classification is done prior to turning on the port. table 17. port mode selection port mode setting b1, b0 mode description 00b shutdown the power is shut down with no detection pulses. a command to manually power the port is ignored. 01b manual the port can be powered by the manual power command. 10b semiauto detection is done and classification is done for rgood, but the port does not power. 11b auto detection classification and port powe ring are all automatic with no host intervention required. i cut and i lim are automatically set according to the poe+ mode and classification result.
si3452 rev. 1.2 19 5.5. command and return registers (registers 0x12?0x1c) the global command register enables manual port turn-on or turn-off, chip reset, port reset, and measurement of port current and v ee . register 0x12 is a write only register. see table 24 on page 24 for a list of all available commands. if the command results in a numerical return value, that value is stored in the measur ement registers, which are read-only. each of the five possible measurements results in a 2 byte return value, and that value is stored in a unique register. v ee is encoded in mv units; so, the full scale is 65.535 v. iport is encoded in 100 a units; so, the full scale is 6.5535 a. the output data is updated by the proper command regist er write operation (see table 23). this means that the numerical value of the port current or v ee voltage in the measurement register will be the value at the time the command was issued. if the port turns off due to an overload or disconnec t, the port current r egister contents will not be set to zero. if a command to read port current is issued and the port is off, the return value will be zero. 5.6. device status register (0x1d) the device event bits are listed in table 18. the device status register is ro. the v ee , uvlo, and overtemp bits reflect the device status. they are set if v ee or temperature is out of range and reset if the v ee or temperature is in range. bit 6 of the interrupt register is set if there is a change in the overtemp status (bit 6 of 0x1d), an d bit 5 of the interrupt register is set if there is a change in the v ee uvlo status (bit 5 of 0x1d). r eading register 0x1d clears these bits of the interrupt register but does not clear the device status register. in addition, bit b0 indicate s whether or not detection ba ck-off is used. for pses that are wired as alternative b (power on the spare pair?typically used for midspans), th e time between detection puls es is increased to slightly over two seconds to avoid interference with alternative a (p ower on the data pair?typically used for endpoints). bit b0 can be toggled using the 0x10 command code. table 18. device status bits bit description b6?overtemp the si3452 has per-port thermal shutdown sensors as well a global thermal shutdown at a slightly higher temperat ure. the global thermal shutdown bit of the device event register is set if this occurs. b5?v ee uvlo v ee uvlo. the part is put in its reset state if v ee is not in a valid range.
si3452 20 rev. 1.2 table 19. si3452 register map address register name type b7 b6 b5 b4 b3 b2 b1 b0 register content at power up interrupts 0x00 interrupt reg 1 ro overtemp change v ee uvlo change port 4 event port 3 event port 2 event port 1 event 0x00 0x01 interrupt mask 1 rw device sta- tus mask t start mask ti cut mask rgood cls mask det compl mask disconnect mask pwrgood mask pwren mask 0x85 port events 0x02 port 1 events cor t start event ti cut event rgood cls det compl disconnect ev pwrgood change pwren change 0x00 0x03 port 2 events cor t start event ti cut event rgood cls det compl disconnect ev pwrgood change pwren change 0x00 0x04 port 3 events cor t start event ti cut event rgood cls det compl disconnect ev pwrgood change pwren change 0x00 0x05 port 4 events cor t start event ti cut event rgood cls det compl disconnect ev pwrgood change pwren change 0x00 status 0x06 port 1 status ro pwrgood status pwrenable status cls stat b2 cls stat b1 cls stat b0 det stat b2 det stat b1 det stat b0 0x00 0x07 port 2 status ro pwrgood status pwrenable status cls stat b2 cls stat b1 cls stat b0 det stat b2 det stat b1 det stat b0 0x00 0x08 port 3 status ro pwrgood status pwrenable status cls stat b2 cls stat b1 cls stat b0 det stat b2 det stat b1 det stat b0 0x00 0x09 port 4 status ro pwrgood status pwrenable status cls stat b2 cls stat b1 cls stat b0 det stat b2 det stat b1 det stat b0 0x00 configuration 1 0x0a port 1 config rw port priority poe+ discon en port mode b1 port mode b0 00000100b 0x0b port 2 config rw port priority poe+ discon en port mode b1 port mode b0 00000100b 0x0c port 3 config rw port priority poe+ discon en port mode b1 port mode b0 00000100b 0x0d port 4 config rw port priority poe+ discon en port mode b1 port mode b0 00000100b 0x0e port 1 i cut rw b7 b6 b5 b4 b3 b2 b1 b0 0x75 notes: 1. register content at power up is shown for the si3452 shutdown mode part. refer to "12. ordering guide" on page 33 to order auto mode parts with different default settings. this register can be changed via the host. refer to table 17 on page 18 for register variations. 2. b0 alternative b timing is set to 0x01 if using alternative b de tect timing. refer to "5.6. device status register (0x1d)" on p age 19 and "12. ordering guide" on page 33.
si3452 rev. 1.2 21 0x0f port 2 i cut rw b7 b6 b5 b4 b3 b2 b1 b0 0x75 0x10 port 3 i cut rw b7 b6 b5 b4 b3 b2 b1 b0 0x75 0x11 port 4 i cut rw b7 b6 b5 b4 b3 b2 b1 b0 0x75 global device 0x12 command reg- ister wo cmd code b5 cmd code b4 cmd code b3 cmd code b2 cmd param b1 cmd param b0 0x00 0x13 v ee msb ro 0x00 0x14 v ee lsb ro 0x00 0x15 current p1 msb ro 0x00 0x16 current p1 lsb ro 0x00 0x17 current p2 msb ro 0x00 0x18 current p2 lsb ro 0x00 0x19 current p3 msb ro 0x00 0x1a current p3 lsb ro 0x00 0x1b current p4 msb ro 0x00 0x1c current p4 lsb ro 0x00 0x1d device status 2 ro overtemp v ee uvlo alternative b timing 0x00 table 19. si3452 register map (continued) address register name type b7 b6 b5 b4 b3 b2 b1 b0 register content at power up notes: 1. register content at power up is shown for the si3452 shutdown mode part. refer to "12. ordering guide" on page 33 to order auto mode parts with different default settings. this register can be changed via the host. refer to table 17 on page 18 for register variations. 2. b0 alternative b timing is set to 0x01 if using alternative b de tect timing. refer to "5.6. device status register (0x1d)" on p age 19 and "12. ordering guide" on page 33.
si3452 22 rev. 1.2 revision 0x60 hardware revision ro 0x61 firmware revi- sion ro 0x62 firmware revi- sion ro 0x63 firmware revi- sion ro table 19. si3452 register map (continued) address register name type b7 b6 b5 b4 b3 b2 b1 b0 register content at power up notes: 1. register content at power up is shown for the si3452 shutdown m ode part. refer to "12. ordering guide" on page 33 to order auto mode parts with different default settings. this register can be changed via the host. refer to table 17 on page 18 for register variations. 2. b0 alternative b timing is set to 0x01 if using alternative b det ect timing. refer to "5.6. device status register (0x1d)" on p age 19 and "12. ordering guide" on page 33.
si3452 rev. 1.2 23 table 20. si3452 detect encoding value condition 000b unknown 001b short 010b reserved 011b rlow 100b good 101b rhigh 110b ropen 111b reserved table 21. si3452 class encoding value condition 000b unknown 001b class 1 010b class 2 011b class 3 100b class 4 101b probes not equal 110b class 0 111b class overload table 22. si3452 port mode encoding value condition 00b shutdown 01b manual 10b semiauto 11b auto
si3452 24 rev. 1.2 table 23. si3452 port configuration poe+ bit class auto mode setting of i cut register i cut nominal ilim nominal* 0 or 1 don?t care 1 0x1e 97 ma 425 ma 0 or 1 don?t care 2 0x35 170 ma 425 ma 0 or 1 don?t care 0/3 0x75 375 ma 425 ma 0 4 0x75 375 ma 425 ma 1 4 0xc9 640 ma 850 ma *note: during initial port turn-on (t start time of 60 ms), the current limit is set to 425 ma, even in poe+ mode. table 24. si3452 command codes command cmd register [b5..b2] [b1..b0] command parameter 2 byte return value power on port 0x04 | port no 0001b 2 bit port number 1 ? power off port 0x08 | port no 0010b 2 bit port number ? reset port 0x0c | port no 0011b 2 bit port number ? toggle detection back-off timing 2 0x10 0100b na ? reset chip 0x14 0101b na ? get v ee 0x18 0110b na v ee in mv units read port current 0x1c | port no 0111b 2 bit port number port current in 100 a units shut down low-priority ports 0x20 1000b na ? notes: 1. port 1 has 2 bit port number 0x00; port 2 is 0x01, etc. 2. this command toggles bit 0 of register 0x1d. when bit zero is set, the detection back-off of 2 seconds is implemented (alternative b or ?midspan? mode).
si3452 rev. 1.2 25 6. operational notes 6.1. port turn on if the port is turned on by putting it in auto mode, the si3452 will take care of all specified timing, and it will take care of the two-event classification if the first event result is class 4 and poe+ mode is enabled. however, if automatic mode operation is not desired after port turn-on, the port should be set to semi-auto or manual mode once it has powered. in automatic mode, i cut is set according to the classification result. the port turn-on command is used to turn on a port in semi -auto or manual mode. if the port is turned on in semi- auto mode, turn-on is delayed until the next detection and cl assification. if the detection or classification result is not valid, the port will not power. if the cl assification is class 4 and poe+ mode is enabled, a 2-event classification is given. i cut setting is not automatic for port turn-on in semi-auto or manual mode. if the port is turned on by putting it in manual mode, the normal sequence is to start wi th the port in semi-auto mode and interrupt on a classification complete, which indicates th at there is a valid pd signature and that a classification result is available. based on the cla ssification result, the host can make a decision to apply power or not. the ieee standard requires that a port be powered within 400 ms of a valid detect complete. it is also desirable to power the port prior to the start of the next detection pulse, which can occur in as little as 300 ms. therefore, it is recommended that ports be powered in under 250 ms from the class complete interrupt when using the manual mode turn-on command. using manual mode turn-on, detection is not done prior to po rt turn on, but classificati on is always performed just prior to port turn on. ports are turned on in manual mode regardless of the classification result. 2-event classification is performed if the first event result is class 4 and the port is enabled for poe+ mode. the manual mode classification step does not generate a classifi cation complete flag because it is assumed that the classification was already done in semi-auto mode and the host has already made the decision to grant power. during the initial 60 ms (tstart) time of port turn-on, 1x current limit and i cut = 375 ma (nominal) is enforced. after tstart, if the port is not overloaded, pgood is set to true, and i cut and 1x or 2x curren t limit will follow the i 2 c register settings. in auto mode, the i 2 c registers are set according to the classification result, but, if desired, they can be overwritten after pgood becomes true. after tstar t, 2x current limit is always allowed if poe+ mode is enabled. 6.2. changing the interrupt mask the int register and int pin are always synchronized. however, there can be up to a 5 ms delay between an event that causes or clears an interrupt and the update of the register and pin. thus, if the int mask register is changed to clear an interr upt or to block an interrupt source, there can be up to a 5 ms delay between the change of the int mask register and the resultant change in the int register and int pin. generally, use of the mask register to clear interrupts is not recommended; it is better to clear an interrupt by reading the appropriate cor register. 6.3. port voltage and current measurements port current voltage and current are reported as of the ti me the measurement command is written to register 0x12. spikes of current or other momentary current changes ar e not filtered. it may be desirable to add a ~1 second averaging filter to reported current when using po rt current information for power management decisions.
si3452 26 rev. 1.2 7. pcb layout guidelines following are some pcb layout considerations. see also "12.1. evaluation kits and reference designs" on page 33 for reference design informat ion. please visit the silicon la bs technical support web page at www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to request support for your design, particularly if you are not closely following the recommended reference design. due to the high current of up to 800 ma per port, the follo wing board layout guidelines apply. in addition, contact silicon laboratories for ac cess to comple te pse reference design databases includ ing recommended layouts. the vee1, vee2, vee3, and vee4 pins can carry up to 800 ma and ar e connected to a v ee bus. the v ee bus for a 24 port pcb layout can thus carry as much as 20 a curr ent. with 2 oz. copper on an outer layer, a bus of 0.4 inches is needed. for an inner layer, th is increases to a 1 inch wide bus. use of large or multiple vias is required for properly supporting the 800 m a per channel operating curr ent. the vee pin does not carr y high current and can be connected directly to the bus as well. the best pr actice is to devote an entire inner layer for v ee power routing. similarly, gnd1/2 and gnd3/4 pins can carry up to 1.6 a per pin, and the gnd return bus should be at least as wide as the v ee bus described above. the best practice is to devote an entire inner layer for ground power routing. the ground power plane does not generally have a high fr equency content (other than external faults); so, it is generally acceptable to use the ground power plane as a ground signal plane and tie agnd and gnd12, gnd34 to this plane as well. the voutn pins carry up to 800 ma dc and up to 5 a in faul ts; so, a 20 mil trace with wide or multiple vias is also recommended. the vdetn pins also carry fault current; so, this pin connection to voutn needs to use 20 mil traces and wide or multiple vias where needed. the vdd currents are not large; so, it is acceptable to route the vdd nodes on one of the outer layers. if care is taken to avoid disruption of the high current pa ths, vdd can be globally rout ed on one of the power planes and then locally routed on an inner or outer layer. to avoid coupling between surge events and logic signals, it is recommended that voutn traces be routed on the side opposite the i 2 c interface pins. the thermal pad of the si3452 is c onnected to vee. at full ieee 802.3at current of 600 ma on each port, the dissipation of the si3452 is up to 1.2 w; so, multiple vi as are required to conduct the heat from the thermal pad to the vee plane. as many as 36 small vias provide the best thermal conduction.
si3452 rev. 1.2 27 8. firmware release notes devices marked with firmware revision 01 (see "13. device marking diagram" on page 34) have the firmware revision registers set as 0x61 = 0x00; 0x62 = 0x02, and 0x63 = 0x4f (0.2.79). the following are known issues, all of which may be addressed with a future firmware revision: 8.1. initialization time issue : the initialization time after a reset or power up is 65 ms. impact : none - informational. workaround : wait 100 ms after a reset before beginning i 2 c transactions. 8.2. current limiting in 2x power mode issue : in 2x current limiting mode, current is limited at the 1x value during the tstart time as required by the 802.3at draft standard. for the last 0.4 ms of the 60 ms tstart time, the current limit is increased to the 2x value. impact : this would only be seen if the pd applies a continuo us overload during the inrush time. the slight extra spike of current is less than 1 m s; so, it falls within the allowed current limit transient response. workaround : none 8.3. i 2 c address ack issue : very rarely, the si3452 may not ack the i 2 c address byte. impact : this is allowed in the i 2 c specification. workaround : retransmit the address byte if there is an ack failure. 8.4. reading or writ ing unused registers it is recommended that unused registers not be read or wr itten. in particular, reads from unused registers can be interpreted as clear on read and may clear unexpected memory locations.
si3452 28 rev. 1.2 9. pin descriptions table 25. si3452 pin descriptions pin # name type description 1 vee1 supply driver 1 vee supply . short to vee, vee2/3/4. 2 vee supply global poe (?48 v nom.) or poe+ (?54 v nom.) supply. short to vee1/2/3/4. 3 vref analog input 1.1 v nom. voltage reference from reference generator (for example, tlv431 or power management unit). 4 ain analog input measurement data converter input. short to aout. 5 aout analog output measurement multiplexer subsystem output. short to ain. 6 agnd ground analog ground reference. short to agnd pin 8, gnd12/34, dgnd. 7 rbias analog input external 44.2 k ? (1%) resistor to ground sets internal bias currents. 8 agnd ground analog ground reference. short to agnd pin 6, gnd12/34, dgnd. 9 nc no connect do not connect (float). 10 vee4 supply driver 4 vee supply . short to vee, vee1/2/3. 11 nc no connect do not connect (float). 12 vout4 analog i/o port 4 power fet switch outp ut. when on, provides a low impedance path to vee4. vee vee1 ain rbias vref agnd aout 1 2 3 4 5 6 7 agnd 8 dgnd vdd ad1 ad3 ad0 ad2 ad2 30 29 28 27 26 25 24 vout4 nc sda nc det4 scl gnd34 11 12 13 14 15 16 17 det3 18 vdd 19 39 38 37 36 35 34 33 vout1 int det1 ad0 rst gnd12 ad1 det2 vee4 10 nc 9 vee3 22 rst 23 ad3 21 vout3 20 32 vout2 31 vee2 si3452 (top view) 40
si3452 rev. 1.2 29 13 det4 analog i/o connection for port 4 detection, cl assification, and transient surge protection. this pin is tied to vout4. 14 sda digital i/o i 2 c data pin 15 gnd34 ground ground supply for protection clamps. short to agnd, gnd12, dgnd. 16 scl digital i/o i 2 c clock pin 17 nc no connect do not connect (float). 18 det3 analog i/o connection for port 3 detection and classification. see det4 for detailed descrip- tion. 19 vdd supply +3.3 v (10%) isolated supply. short to vdd pin 30. 20 vout3 analog i/o port 3 power fet switch outp ut. when on, provides a low impedance path to vee3. 21 ad3 digital i/o chip address bit 3 pin, read after reset. address set with defined resistor dividers. pin also used for internal commu nications. short to ad3 pin 24. 22 vee3 supply driver 3 vee supply . short to vee, vee1/2/4. 23 rst digital input active low digital reset. short to rst pin 38. 24 ad3 digital i/o chip address bit 3 pin, read after reset. address set with a 10 k ?? pull-up or pull- down resistor. also used for internal communications. short to ad3 pin 21. 25 ad2 digital i/o chip address bit 2 pin, read after reset. address set with a 10 k ?? pull-up or pull- down resistor. also used for internal communications. short to ad2 pin 26. 26 ad2 digital i/o chip address bit 2 pin, read after reset. address set with a 10 k ?? pull-up or pull- down resistor. also used for internal communications. short to ad2 pin 25. 27 ad1 digital i/o chip address bit 1 pin, read after reset. address set with a 10 k ?? pull-up or pull- down resistor. also used for internal communications. short to ad1 pin 36. 28 ad0 digital i/o chip address bit 0 pin, read after reset. address set with a 10 k ?? pull-up or pull- down resistor. also used for internal communications. short to ad0 pin 34. 29 dgnd ground digital ground refere nce. short to agnd, gnd12/34 30 vdd supply +3.3 v isolated supply. short to vdd pin 19. 31 vee2 supply driver 2 vee supply . short to vee, vee1/3/4. 32 vout2 analog i/o port 2 power fet switch outp ut. when on, provides a low impedance path to vee2. 33 det2 analog i/o connection for port 2 detection and classification. see det4 for detailed descrip- tion. 34 ad0 digital i/o chip address bit 0 pin. see description for- and short to ad0 pin 28. 35 gnd12 ground ground supply for protection clamps. short to agnd, gnd34, dgnd. 36 ad1 digital i/o chip address bit 1 pin. see description for- and short to ad1 pin 27. table 25. si3452 pin descriptions (continued) pin # name type description
si3452 30 rev. 1.2 37 det1 analog i/o connection for port 1 detection and classification. see det4 for detailed descrip- tion. 38 rst digital input active low digital reset. short to rst pin 23. 39 vout1 analog i/o port 1 power fet switch outp ut. when on, provides a low impedance path to vee1. 40 int digital output active low interrupt output pin. epad vee supply connect the thermal pad to a plane which connects to vee. for best results, use a 5 x 5 or larger via array for best thermal co nductivity with 1 square inch or larger of plane area per device. table 25. si3452 pin descriptions (continued) pin # name type description
si3452 rev. 1.2 31 10. package out line: 40-pin qfn the si3452 is packaged in an industry -standard, rohs compliant 6 x 6 mm 2 , 40-pin qfn package. figure 7. 40-pin qfn mechanical diagram table 26. package diagram dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 6.00 bsc. d2 3.95 4.10 4.25 e 0.50 bsc. e 6.00 bsc. e2 3.95 4.10 4.25 l 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline mo-220, variation vjjd-2 4. recommended card reflow profile is per the jedec/ipc j-std-02 0 specification for small body components.
si3452 32 rev. 1.2 11. recommended pcb footprint figure 8. pcb land pattern table 27. pcb land pattern dimensions dimension min max e 0.50 bsc e5 . 4 2 r e f d5 . 4 2 r e f e2 4.00 4.20 d2 4.00 4.20 ge 4.53 ? gd 4.53 ? x ? 0.28 y0 . 8 9 r e f ze ? 6.31 zd ? 6.31 notes: general 1. all dimensions shown are in mill imeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on ipc-sm-782 guidelines. 4. all dimensions shown are at maximum materi al condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. solder mask design 5. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 6. a stainless steel, laser-cut and electro-polished st encil with trapezoidal wa lls should be used to assure good solder paste release. 7. the stencil thickness should be 0.125 mm (5 mils). 8. the ratio of stencil aperture to land pad si ze should be 1:1 for the perimeter pads. 9. a 4x4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center vee pad. card assembly 10. a no-clean, type-3 solder paste is recommended. 11. the recommended card reflow profile is per t he jedec/ipc j-std-020 specification for small body components.
si3452 rev. 1.2 33 12. ordering guide 12.1. evaluation kits and reference designs ordering part number 1 detect timing 2,5 powerup mode 2,3,4,5 firmware revision package 6 temp. range si3452-b01-gm alt a poe 7 shutdown 0.2.79 ?40 to 85 c ambient si3452a-b01-gm alt a poe (15.4 w) auto si3452b-b01-gm alt b SI3452C-B01-GM alt a poe+ (30 w) si3452d-b01-gm alt b notes: 1. add ?r? to the end of the ordering part number to denote tape-and-reel optio n. e.g., si3452-b01-gmr. 2. for alternative a, power is applied to wire pairs 1,2 and 3,6. for alte rnative b, power is applied to wire pairs 4,5 and 7,8 (the spare pairs in the case of 10/100 et hernet). conventionally, alternative b is used for midspan power injectors. for alternative b, detection is done with over 2 seconds between de tection pulses so as to avoid interfering with end-point equipment trying to provide power using alternative a. 3. devices powering up into shutdown mode ar e intended for use with a system host that provides run- time configuration or power-management. 4. the maximum poe or poe+ power applies to all ports on auto mode devices. 5. detect timing and powerup modes (poe vs. poe+, shutdow n vs. auto) are pre-configured in firmware but can be reconfigured at any time via a host connection. 6. all devices are packaged in rohs-compliant, 40-pin, 6x6 mm qfn. 7. the si3452-b01-gm is poe+ capable. the part defaults to po e mode at powerup but can be reconfigured to poe+ via register settings. part number populated device description related ethernet chipset type si3452ms8-kit si3452-b01-gm poe+ 8-port midspan pse evalua- tion kit. includes pc-control inter- face, pd loads, and cables. none evaluation kit si3452v1-rd* si3452-b01-gm poe/poe+ 24-port daughtercard vitesse e-stax (vsc7407) reference design si3452v2-rd* si3452-b01-gm poe+ 8-port gb-ethernet switch vitesse sparx-g8e (vsc7398) reference design si3452m1-rd* si3452-b01-gm poe/poe+ 24-port daught ercard marvell prestera-d x, xcat reference design *note: due to unique high-voltage and high-power design cons iderations, silicon laboratories recommends that the reference designs be followed very closely for both bill of materials and layout. please visit the silicon labs technical support web page at www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to request support for your design, particularly if you are not closely following the recommended reference design.
si3452 34 rev. 1.2 13. device marking diagram figure 9. device marking diagram table 28. device marking table line # text value description 1 si3452 base part number. this is not the ?ordering part number? since it does not contain a specific revision. refer to "12. ordering guide" on page 33 for complete ordering information. 2x z z x = device revision. zz = firmware revision. 2g m g = industrial temperature range. m = qfn package. 3 tttttt trace code (assigned by the assembly subcontractor). 4 o pin 1 identifier. yy assembly year. ww assembly week. ? ?
si3452 rev. 1.2 35 d ocument c hange l ist revision 1.0 to revision 1.1 ? updated -gm parts temperature range to ?40 to +85 c, eliminating the need for the -im ordering part numbers. contact silicon labs for date code information if needed. revision 1.1 to revision 1.2 ? removed references to si3453 throughout. ? updated figure 9, ?device marking diagram,? on page 34. ? updated typical v dd reset threshold in table 3 on page 5. ? clarified notes in table 19, ?si3452 register map,? on page 20. ? updated table 28, ?device marking table,? on page 34. ? clarified notes in "12. ordering guide" on page 33.
si3452 36 rev. 1.2 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsibi lity for any consequences resu lting from the use of information included herein. ad ditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including wi thout limitation conse- quential or incidental damages. si licon laboratories products are not designed, in tended, or authorized for use in applications intended to support or sustain life, or for any other application in whic h the failure of the silicon labor atories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or use silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmles s against all claims and damages.

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